This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems which receive a stream of requests to perform respective processing tasks and to generate corresponding blocks of result data values to be output as part of a result data stream.
There are many situations in which a data processing system may receive a stream of requests to perform respective processing tasks to generate corresponding blocks of result data values. One example of such systems is a graphics processing pipeline in which a vertex transformation stage receives requests to perform transform operations upon received vertex data to form transformed vertex data. The requests correspond to a stream of vertex data to be transformed and the blocks of result data correspond to a stream of transformed vertex data that is generated. In such embodiments, the stream of transformed vertex data is typically directly passed to a subsequent rasterization stage. A wide bus is used to pass the large volumes of data that is so generated. However, if a deferred rendering approach is adopted, then the transformed vertex data needs to be stored to memory before it is subsequently read by the rasterization stage. The large volumes of data which need to be transferred to and from memory in such situations represent a significant overhead in terms of both speed and power consumption.